IC Compiler 1 培訓

• Perform data setup, which includes loading required synthesis and physical data, creating a Milkyway design library, and applying common timing and optimization controls
• Create a non-hierarchical chip-level floorplan that will be routable and will achieve timing closure
• Perform placement and related optimizations to minimize timing violations, congestion, and power
• Analyze congestion maps and timing reports
• Perform pre-CTS power optimization
• Perform clock tree synthesis
• Analyze clock and timing results post-CTS
• Route the clock nets
• Execute a Zroute-based signal routing flow, with concurrent via doubling and antenna fixing
• Analyze and fix physical DRC and LVS violations
• Perform functional ECOs
• Perform chip finishing steps
• Generate output files required for final validation/verification

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IC Compiler 1 培訓

課程內容：